1. Field of the Invention
The present invention relates to semiconductor manufacturing, and in particular relates to a method for forming a via.
2. Description of the Related Art
The plasma etching technique and methods thereof, was first used to manufacture devices in 1970. And its principle has been understood and realized. For present integrated circuit manufacturing, various materials used must have the capability to be appropriately controlled at sub-micro levels with high reproducibility. Since the plasma etching method is the only effective way for etching that can be performed with high productivity, it is still a major method used in integrated circuit manufacturing.
The plasma etching method has advantages of anisotropism and having a high selective ratio. In the plasma etching process, the high selective ratio is achieved due to chemical reaction. Re-deposited production or polymer is formed on the expected etched pattern. A portion of the deposition, formed on the surface of the pattern, is continuously removed by ions, and thus etched. A portion of the deposition, formed on the side wall of the pattern is maintained to prevent ions from etching the side wall of the pattern. Therefore, achieving anisotropic etching. Plasma etching is a popular method for forming a high aspect ratio via needed for present integrated circuit devices. By using the physical attacking and chemical etching effects, controlled by plasma conditions and gas chemical compounds, the desired anisotropic and selective etching method can be used to obtain a via with vertical side walls.
However, due to demand for even lower scale and higher density integrated circuit fabrication, it is possible, when using the conventional plasma etching method, for a un-landing via 190 to be formed on a top surface of a conductive structure 100 as shown in FIG. 1A. The effect results from a discrepancy in disposition of the via due to a slight shift in the mask pattern. The un-landing via 190 causes a micro-trench 191 in a dielectric layer 120. FIG. 1B shows an enlarged view of the micro-trench 191. An angle θ between the bottom 102 (which is adjoined with the conductive structure, and has a tangent line A) of the micro-trench 191 and the sidewall 101 of the conductive structure is small (between about 5° to about 40°).
Thus, the micro-trench 191 easily becomes a dead space for subsequent material deposition processes. In addition, etched residue or impurities deposited in the micro-trench 191 can not be easily removed.
Furthermore, for etching a via with a desired depth, or avoiding insufficient depth of the via, parameters, according to the conventional etching method, are set according to the condition for forming a via with a depth deeper than the desired value. Referring to FIG. 1A, the via 190, formed by the conventional etching method, has a deep depth. Thus, a big area portion of the sidewall of the conductive structure 100 is exposed in the etching environment, resulting in increased destructible ratio of the conductive structure 100. Therefore, influencing the electric property such as electromigration reliability or RC of the device.
The conventional etching method has limited application when demanding high precision features and excellent electric properties of devices. As such, a novel fabrication method for forming a via is needed.